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Bump Mill 0.11.1, Scala 2.13.10, and Chisel 3.6.0 #67

Merged
merged 1 commit into from
Oct 9, 2023
Merged

Bump Mill 0.11.1, Scala 2.13.10, and Chisel 3.6.0 #67

merged 1 commit into from
Oct 9, 2023

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@poemonsense poemonsense marked this pull request as draft October 8, 2023 12:58
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poemonsense commented Oct 8, 2023 •
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@sequencer Our CI fails because the top-level IOs does not have user bits anymore. Previously it works. We believe passing requestFields to TLMasterPortParameters with make IOs should create the corresponding user bits in IO. Is it? Do you have any idea why we don't have the IO anymore? I look into the code but have not found anything yet. It would be great if you know whether we can check to debug this. Fixed by #68

Here is our code for specifying the user bits:

CoupledL2/src/test/scala/TestTop.scala

Lines 304 to 317 in 4fef1f2

TLMasterPortParameters.v2(
masters = Seq(
TLMasterParameters.v1(
name = name,
sourceId = IdRange(0, sources),
supportsProbe = TransferSizes(cacheParams.blockBytes)
)
),
channelBytes = TLChannelBeatBytes(cacheParams.blockBytes),
minLatency = 1,
echoFields = Nil,
requestFields = Seq(AliasField(2)),
responseKeys = cacheParams.respKey
)

@poemonsense poemonsense marked this pull request as ready for review October 9, 2023 04:17
@poemonsense poemonsense merged commit bf0b6b6 into master Oct 9, 2023
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@poemonsense poemonsense deleted the bump-3.6 branch October 9, 2023 05:06
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@poemonsense @wakafa1